1. Field of the Invention
The present invention relates to a memory control system employing at least one clock synchronous memory which is controlled by a memory control unit or the like, and to a memory control method for controlling the clock synchronous memory. More particularly, this invention is concerned with a memory control system and memory control method in which, when numerous memories must be provided in order to secure a memory space for a large storage capacity, access to the numerous memories can be made quickly.
In recent years, a capability of a microprocessor (usually abbreviated to MPU (microprocessor unit)) for processing various data has improved remarkably. A storage unit (or memory circuit) which is to be included in a system employing such a microprocessor is likely to be required to have a large storage capacity and to be quickly accessible. With regard to a memory or memories constituting a storage unit satisfying the above requirement, a novel DRAM such as a synchronous dynamic random access memory operating synchronously with a clock (hereinafter abbreviated to SDRAM) has been developed. The SDRAM operates synchronously with a high-frequency clock having a frequency equal to 100 MHz or more than 100 MHz and can input or output data requested by the microprocessor or the like.
A memory control unit including a microprocessor is designed to control the SDRAM. An idea of a maximum driving capacity to drive a memory is discussed with regard to the memory control unit. A value indicating the maximum driving capacity generally restricts the number of SDRAMs that can be connected to the memory control unit. Owing to the restriction in the number of SDRAMs and a storage capacity of each SDRAM which is to be employed, the total capacity that can be provided as a system is determined. However, available types of SDRAMs are limited to some types. For realizing the system having a large storage capacity by using these SDRAMs, it is necessary to increase the number of SDRAMs which are to be employed.
2. Description of the Related Art
For better understanding of the problems underlying memory control systems according to the prior art, typical configurations of conventional memory control systems will be described with reference to FIGS. 1 and 2 that will be later mentioned in "DESCRIPTION OF THE DRAWINGS." The configurations of the conventional memory control systems will be schematically shown in the form of circuit block diagrams.
In a memory control system of the first prior art shown in FIG. 1, an SDRAM control unit (SDRAM controller) 200 is included as a memory control unit for controlling SDRAMs. A plurality of SDRAMs 11 is connected to the SDRAM control unit 200. Data DATA (for example, data DATA [00:31] or data DATA [32:64] of 64 bits long) is input or output to or from the SDRAM control unit 200 and SDRAMs 11 synchronously with a clock CLK. The clock CLK is generated by the SDRAM control unit 200.
In the SDRAM control unit 200, not only the clock CLK but also various control signals and a data mask signal DQM are generated and supplied to the SDRAMs 11 through a signal input/output port 210. Herein, the various control signals are used to control the SDRAMs 11 and the data mask signal DQM is used to mask data DATA. The various control signals include an address signal ADR, a low-address strobe signal /RAS (signal of negative logic), a column address strobe signal /CAS (signal of negative logic), a write enable signal /WE (signal of negative logic), a bank address signal BA, a chip selection signal /CS (signal of negative logic), and a clock enable signal CKE.
In the configuration in which the SDRAMs 11 are connected directly to the SDRAM control unit 200, as mentioned above, the largest load is imposed on an input/output port for outputting various control signals. The maximum driving capacity of the SDRAM control unit 200 is therefore restricted by an input/output port for outputting control signals. The number of SDRAMs that can be connected to the SDRAM control unit is determined by the maximum driving capacity of the SDRAM control unit 200.
Assume, as shown in FIG. 1, that the number of SDRAMs that can be connected to the SDRAM control unit is 4. A semiconductor product having a storage capacity of 64 megabits (M bit) is adopted as SDRAMs which are to be included in a memory control system, whereby a memory space having a data width of 64 bits is realized. In this case, the storage capacity of the memory space is given as follows:
64 megabits.times.4=256 megabits=32 megabytes (M Byte)
For improving the maximum driving capacity of an SDRAM control unit, a buffer may be inserted to the output stage of an input/output port. Herein, the buffer operates to compensate for the maximum driving capacity.
The circuit block diagram of FIG. 2 shows a memory control system of the second prior art which is conceived of the basis of the above-mentioned technical idea.
In the memory control system of the second prior art shown in FIG. 2, a buffer 300 is interposed between an input/output port 210 of an SDRAM control unit 200 for outputting control signals and SDRAMs 11. The buffer 300 is composed of a plurality of buffer circuits and is used to improve the maximum driving capacity of the SDRAM control unit 200. Thus, the number of SDRAMs that can be connected to the SDRAM control unit can be increased. For example, in the memory control system shown in FIG. 2, since the maximum driving capacity of the SDRAM control unit becomes four times as large as that in the memory control system shown in FIG. 1, the number of SDRAMs that can be connected to the SDRAM control unit can be increased up to 16. Eventually, the storage capacity of an entire memory space also becomes four times (for example, 128 megabytes) as large as that in the memory control system of the first prior art shown in FIG. 1.
However, the fact that the buffer is included in the memory control system shown in FIG. 2 causes a delay in various control signals (an address signal ADR, row address strobe signal /RAS, column address strobe signal /CAS, write enable signal /WE, bank address signal BA, chip selection signal /CS, clock enabling signal CKE, and data mask signal DQM). For controlling especially the SDRAMs that are required to operate at high speed, it becomes difficult to adjust the difference of the timing between different control signals which are output from buffer circuits in the buffer. That is to say, it becomes difficult to adjust a skew occurring between different control signals.
As mentioned above, when a memory control system is realized by employing SDRAMs or the like, the storage capacity of an entire memory space is determined dependent on the type of SDRAMs which are to be employed, and the number of SDRAMs which can be driven by a memory control unit for controlling the SDRAMs. However, the available types of SDRAMs are limited. For realizing a memory space for a large storage capacity by employing SDRAMs, it is therefore necessary to increase the number of SDRAMs which are to be employed.
However, as is apparent from FIG. 1 showing the memory control system of the first prior art, the number of SDRAMs that can be connected to a memory control unit for controlling the SDRAMs is limited. More specifically, the number of SDRAMs depends on a performance of an input/output port of the memory control unit. Further, the number of SDRAMs depends on a capacity of the input/output port concerning a load which can be connected thereto.
By the way, as seen from FIG. 2 showing the memory control system of the second prior art, a technique for increasing the number of SDRAMs that can be driven by a memory control unit is conceivable. Namely, an input/output buffer is connected between the memory control unit and SDRAMs so as to increase the capacity concerning the load which can be connected to the input/output port.
The adoption of the technique implemented in the second prior art requires a design in which a delay of each control signal caused by the connection of the input/output buffer and skews occurring between a plurality of control signals are taken into account. However, SDRAMs connected to the memory control unit are required to operate at higher speed year by year, and therefore it becomes difficult to adjust these skews caused by including a buffer. Therefore, a problem occurs in that even if the number of SDRAMs that can be connected to the memory control unit is increased, access to the SDRAMs cannot be made quickly, and it becomes difficult for the SDRAMs to operate at relatively high speed.